This module is designed specifically for the Banana Pi IO expansion modules, which can effectively solve the banana send IO port insufficient. Module uses four 74HC595 chips to expand 32 IO ports. As shown above, the top of the module will expand the IO of Banana Pi again that can be cascaded for more IO expansion modules can theoretically unlimited expansion.
- Expanded 32 GPIO
- Infinity connection for the same module
- Use wiringPi API ,sample code
- Banana Pi 2X13 port
- Banana Pi 2X13 cascade port
- Q0-Q31 expanded IO port
- Working voltage: 2.4V-5V
- IO voltage: 3.3V
- Expanded 32 unidirectional IO
- Connection through SPI
- 100 MHz (typical) shift out frequency
- 8-bit serial input
- 8-bit serial or parallel output
- Specified from -40C to +85C and from -40C to +125C
- Drive the lattice screen
- Driver numeric display
- Drive matrix LED
Insert the module that the silk screen says “BPI IN”. Pay attention don’t make the direction reversed! The correct direction of insert module is above the Banana Pi’s PCB; The 8*4header in the module are Q0-Q31 expanded GPIO, they can connect to the peripheral through the Dupont Line. The header which near silk screen write ”EXT” expand GPIO of Banana Pi, user can cascade the other module or the same module.
The 74HC595; 74HCT595 are high-speed Si-gate CMOS devices and are pin compatible with Low-power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard No. 7A.
The 74HC595; 74HCT595 are 8-stage serial shift registers with a storage register and 3-state outputs. The registers have separate clocks.Data is shifted on the positive-going transitions of the shift register clock input (SHCP). The data in each register is transferred to the storage register on a positive-going transition of the storage register clock input (STCP). If both clocks are connected together, the shift register will always be one clock pulse ahead of the storage register.
The shift register has a serial input (DS) and a serial standard output (Q7S) for cascading. It is also provided with asynchronous reset (active LOW) for all 8 shift register stages. The storage register has 8 parallel 3-state bus driver outputs. Data in the storage register appears at the output whenever the output enable input (OE) is LOW.
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